1. Field of the Invention
The present invention relates to a semiconductor storage device having four-transistor memory cells to save an area.
2. Description of the Related Art
Conventionally, a memory cell of a static random access memory (SRAM) is provided with two access transistors and four driver transistors.
As such an SRAM device, the one with access at a higher speed is proposed (Japanese Patent Laid-Open Publication No. Hei 9-270468). In the conventional SRAM device disclosed in this publication, gate electrodes of six transistors constituting one memory cell are extended substantially in the same direction. Consequently, access can be performed at a high speed since an occupied area of the memory cell is reduced and the bit line length is shortened. Two access transistors in one memory cell are disposed at either end parts of the memory cell, respectively, in the longitudinal direction. Each access transistor is provided with contact plugs for supplying signals from word lines (metal interconnect lines) in the upper layer. Bit lines are extended in the short direction of the memory cell while word lines are extended in the direction perpendicular thereto.
An SRAM device with a reduced element area has been proposed (Japanese Patent Laid-Open Publication No. Hei 10-178110). In the conventional SRAM device disclosed in this publication, gate electrodes of six transistors constituting one memory cell are also extended substantially in the same direction. Two access transistors in one memory cell are disposed at either end parts, respectively, of the memory cell in the longitudinal direction. Contact plugs for supplying signals from word line (metal interconnect line) in the upper layer to the access transistors are shared between two neighboring memory cells. Therefore, two memory cells have two contact plugs each. In this conventional SRAM device, word lines are extended in the longitudinal direction of the memory cell while the bit lines are extended in the direction perpendicular thereto.
Recently, an SRAM cell composed of four transistors has been proposed (Japanese Application Publication No. Hei 10-346149). FIG. 1 is a circuit diagram showing a conventional SRAM cell.
In the conventional SRAM cell composed of four transistors, in one memory cell provided are access transistors Tr101 and Tr102 of which sources are connected to two bit lines BL101 and BL102, respectively, constituting a bit line pair. The access transistors Tr101 and Tr102 are p-channel MOS transistors. A word line WL101 is connected to respective gates of the access transistor Tr101 and Tr102.
Also provided is a driver transistor Tr103 of which drain is connected to the drain of the access transistor Tr101 and of which gate is connected to the drain of the access transistor Tr102. Further provided is a driver transistor Tr104 of which drain is connected to the drain of the access transistor Tr102 and of which gate is connected to the drain of the access transistor Tr101. The driver transistor Tr103 and Tr104 are n-channel MOS transistor. The sources of the driver transistor Tr103 and Tr104 are grounded.
FIG. 2A is schematic view showing a relationship between a gate electrode and a diffused layer in each transistor of the conventional SRAM cell and the contact plugs connected thereto. FIG. 2B is a schematic view showing a relationship between a first metal interconnect layer of the conventional SRAM cell and the contact plugs connected therebeneath. FIG. 3 is a sectional view along line Cxe2x80x94C in FIGS. 2A and 2B.
In the conventional SRAM cell, as shown in FIG. 2A, the access transistors Tr101 and Tr102 are disposed side by side in the short direction at one end part in the longitudinal direction. The driver transistors Tr103 and Tr104 are disposed in this order over the end part on the side opposite to the side of the access transistors Tr101 and Tr102 in the longitudinal direction.
This conventional SRAM cell is provided with a gate poly-silicon layer G101 constituting the gate electrodes of the access transistor Tr101 and Tr102. The gate poly-silicon layer G101 is extended in the short direction of the cell. The gate poly-silicon layer G101 is shared among a plurality of SRAM cells arrayed in the short direction and constitutes the word line WL101 of these SRAM cells. Further, gate poly-silicon layers G103 and G104 are provided to constitute the gate electrodes of the driver transistors Tr103 and Tr104, respectively.
In addition, a contact plug CS101 is provided on a source diffused layer S101 of the access transistor Tr101 and a contact plug CD101 is provided on a drain diffused layer D101 of the access transistor Tr101. Similarly, a contact plug CS102 is provided on a source diffused layer S102 of the access transistor Tr102 and a contact plug CD102 is provided on a drain diffused layer D102 of the access transistor Tr102. A contact plug CS103 is provided on a source diffused layer S103 of the driver transistor Tr103 and a contact plug CD103 is provided on a drain diffused layer D103 of the driver transistor Tr103. Furthermore, a contact plug CS104 is provided on a source diffused layer S104 of the driver transistor Tr104 and a contact plug CD104 is provided on a drain diffused layer D104 of the driver transistor Tr104.
The gate poly-silicon layer G103 is connected to the drain diffused layer D102 of the access transistor Tr102 via the contact plug CD102 and connected to the drain diffused layer D104 of the driver transistor Tr104 via the contact plug CD104. The gate poly-silicon layer G104 is connected to the drain diffused layer D101 of the access transistor Tr101 via the contact plug CD101 and connected to the drain diffused layer D103 of the driver transistor Tr103 via the contact plug CD103.
As shown in FIG. 3, a sidewall insulating layer 102 is formed on the side of each gate poly-silicon layer except for portions with which the contact plugs are in contact. A gate oxide film 105 is formed between each gate poly-silicon layer and the p-type semiconductor substrate 101. An n-well 104 is formed at the surface of a semiconductor substrate 101 in a region in which the access transistors Tr101 and Tr102 are provided. Further, an embedded field insulating layer 103 is selectively formed between the transistors. First and second interlayer insulating layers 151 and 152 for coating the entire surface of these gate poly-silicon layers, diffused layers and the like are formed in this order. The contact plugs CD101, CD102, CD103 and CD104 provided on the drain diffused layer of each transistor are formed only in the first interlayer insulating layer 151.
Furthermore, as shown in FIGS. 2B and 3, a first metal interconnect layer 161 is provided on the second interlayer insulating layer 152. A ground layer 112 connected to the contact plugs CS103 and CS104 is formed in the first metal interconnect layer 161. Interconnect layers 113a and 113b connected to the contact plug CS101 and CS102, respectively, are also formed in the first metal interconnect layer 161.
Furthermore, a third interlayer insulating layer 153 is formed on the second interlayer insulating layer 152 and first metal interconnect layer 161. Through holes are formed at positions coinciding with the interconnect layers 113a or 113b in the third interlayer insulating layer 153 and conductive layers 114 are embedded in the through holes. Further, as shown in FIG. 3, a second metal interconnect layer 162 is provided on the third interlayer insulating layer 153. Two bit lines BL101 and BL102 connected to each conductive layer 114 are formed in the second metal interconnect layer 162. The bit lines BL101 and BL102 are extended in the longitudinal direction of the cell and are shared among a plurality of SRAM cells disposed along the direction.
The threshold voltage of the driver transistors Tr103 and Tr104 is set higher than that of the access transistors Tr101 and Tr102 by, for example, about 0.1-0.6 V.
In the conventional SRAM cell constituted as described above, an SRAM cell can be constituted by four transistors since the threshold value of each transistor is appropriately prescribed. As a result, the occupied area can be substantially reduced compared with the one using six transistors.
In the above-described conventional SRAM cell constituted by four transistors, however, the expected object is achieved, but saving the area is not enough to respond to the recent further circuit integration. In addition, there is a problem that the recent increase of operation speed cannot be sufficiently responded.
Furthermore, there is also a problem that it is extremely difficult to control the shape of a diffused layer to the designed shape in actual manufacturing processes in the SRAM cells described in the aforementioned Japanese Patent Laid-Open Publication No. Hei 9-270468 and Japanese Patent Laid-Open Publication No. Hei 10-178110.
An object of the present invention is to provide a semiconductor storage device provided with four-transistor memory cells capable of reducing the occupied area and improving the operation speed.
A semiconductor storage device according to the present invention comprises two bit lines, a first transistor of a first conductive type, a second transistor of the first conductive type, a third transistor of a second conductive type and a fourth transistor of the second conductive type. Sources of the first and second transistors are connected to the two bit lines, respectively. The first and second transistors are disposed in a channel width direction thereof and in the longitudinal direction of the four-transistor memory cell on a semiconductor substrate. A drain of the third transistor is connected to a drain of the first transistor, a gate of the third transistor is connected to a drain of the second transistor and a source of the third transistor is grounded. A drain of the fourth transistor is connected to the drain of the second transistor, a gate of the fourth transistor is connected to the drain of the first transistor and a source of the fourth transistor is grounded.
According to the present invention, in the semiconductor storage device having four-transistor memory cells, the first and second transistors connected to the bit line pair are disposed in the direction of the channel width thereof and in the longitudinal direction of the four-transistor memory cells on the semiconductor substrate. Therefore, it is possible to extend a source/drain diffused layers of each transistor in the short direction to reduce the occupied area. Consequently, a word line can be extended in the longitudinal direction while bit lines can be extended in the short direction. As a result, high-speed operation can be achieved due to reduction of the bit line capacitance.
If a word line composed of a metal layer is provided, resistance and capacitance of the word line are reduced and thereby further high-speed operation can be achieved.
In addition, if bit lines are disposed to extend in the short direction, the bit line length is substantially shortened and thereby further high-speed operation can be achieved.
The nature, principle, and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.